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GaN-on-Diamond and the Thermal Ceiling of the AI Compute Era: The Bottleneck Is the Interface, Not the Diamond

NVIDIA's own reference architecture now budgets up to 142 kW for a single GB300 NVL72 rack, while the modal rack in the global installed base still sits near 9 kW — an order-of-magnitude split between the frontier and the installed base. Liquid cooling solves transport at rack level; the real ceiling is the last millimetre between junction and cold plate. Copper, SiC and AlN have run out of headroom, diamond is an order of magnitude above them, and yet most of that advantage is consumed by thermal boundary resistance. This piece works through the published record on GaN-on-diamond (11 W/mm at 10 GHz, >3.5x areal power density, TBR driven from ~220 down to ~3.1 m²K/GW), the single-crystal versus polycrystalline split in near-interface conductivity (measured grain conductivity of 638 W/m·K against >2000 for bulk grades), and what all of this means for material suppliers: the spec sheet is shifting from carat and colour to thickness tolerance, bondable surfaces and lot-to-lot consistency.

GaN on diamond2026-07 · 10 min

01Conclusion first: the ceiling has moved from grid power to the last millimetre

The judgement up front: the binding constraint on AI compute is shifting from securing grid power to moving heat across the last millimetre. NVIDIA's enterprise reference architecture specifies a GB300 NVL72 rack drawing up to 142 kW, fully liquid cooled, fed by eight 33 kW power shelves of six 5.5 kW PSUs each. Uptime Institute's 2025 global survey, meanwhile, finds that more than 80% of operators report no racks above 30 kW at all, with modal rack density around 9 kW, up from 8.3 kW a year earlier. That is an order-of-magnitude gap between the frontier and the installed base. Rack-level liquid cooling addresses transport from cold plate to facility; junction temperature is set by the sub-millimetre stack beneath it — epilayer, interlayer, bond, spreader. And junction temperature sets lifetime: BAE Systems, a participant in DARPA's NJTT and ICECool programmes, reported at CS MANTECH that a 10°C reduction in junction temperature yields roughly a 5x improvement in device lifetime for a typical GaN process (activation energy ~2 eV). That arithmetic is why diamond is being repriced — and it frames the argument here: this race will be won at the interface, not in the bulk conductivity of diamond.

02The real shape of the power-density curve: bifurcation, not a rising average

The most common misreading of the public data is to treat AI power density as an average that is drifting upward. The IEA's Energy and AI analysis sets the macro frame: data centres consumed roughly 415 TWh in 2024, about 1.5% of global electricity, and are projected to roughly double to about 945 TWh by 2030 in the base case — just under 3% of global demand, growing around 15% per year, with accelerated servers growing about 30% annually and accounting for nearly half of the net increase. The micro distribution, however, is bifurcated. New AI factories are engineered around hundred-kilowatt racks with mandatory liquid cooling, while the modal rack in the installed base remains below 10 kW; Uptime finds only about one facility in eight hosting racks in the 30–59 kW band, and cabinets above 100 kW remain rare. Thermal value is therefore not spread across an 'average' data centre — it concentrates in a small number of extreme nodes. The same IEA report notes cooling accounts for roughly 7% of total consumption in efficient hyperscale sites but over 30% in less efficient enterprise facilities. Heat removal is part of the compute economics, not a line item at the end of the opex table.

03Why copper, SiC and AlN have run out: magnitude, temperature roll-off and CTE

The conductivity gap is structural. A 2023 Micromachines review of thermal boundary resistance in GaN devices lists the working values: silicon around 130 W/m·K, SiC around 490 W/m·K, diamond 800–2000 W/m·K — while amorphous silicon nitride, the dielectric that often sits at the critical interface, comes in at just 1–1.9 W/m·K. Element Six's handbook is more granular: polycrystalline thermal grades TM100/TM150/TM180/TM200 are specified at >1000/>1500/>1800/>2000 W/m·K at 300 K, and single-crystal MCC grade at >1900 W/m·K. Two engineering caveats are routinely ignored. First, temperature roll-off: in the same handbook, at 425 K (about 152°C) both TM180 and TM200 fall back to >1500 W/m·K, as does single-crystal MCC. Designing against a room-temperature figure of 2000 is systematically optimistic. Second, thermal expansion: diamond's CTE is about 1.0 ppm/K at 300 K — close to GaN and SiC but far from copper. That mismatch is simultaneously why diamond can sit next to the die and why bonded stacks crack. For copper, the defensible public comparisons are relative: Akash Systems states diamond removes heat about 5x faster than copper, and Element Six notes that even finer-grain, 140 mm free-standing polycrystalline wafers still exceed 2.5x copper. AlN-class ceramics sit another order of magnitude below diamond.

04What GaN-on-diamond has actually delivered: RF first, compute now spilling over

This is not a concept: there is more than a decade of verifiable data. Under DARPA's Near Junction Thermal Transport and ICECool programmes, BAE Systems and partners reported at CS MANTECH 2016 that GaN-on-diamond transistors delivered up to 11 W/mm at 10 GHz, with transistor-level areal power density more than 3.5x that of GaN-on-SiC — achieved by packing three times the gate fingers into the same mesa area. Infrared imaging showed peak temperatures about 7°C lower than the GaN-on-SiC control. Combined with embedded microchannel cooling, MMICs sustained waste heat flux above 1 kW/cm² while holding junction temperature below 240°C, with a a simulated thermal resistance of 22.4 K·cm²/kW (1000 W/cm² heat flux, 2.84 L/min·cm² areal flow). The industrial track is equally documented: Element Six transferred its GaN-on-diamond epiwafer technology to Korea's RFHIC in 2017; Akash Systems, which grew out of satellite RF, announced diamond-cooled AMD Instinct MI350X AI servers with MiTAC in March 2026, claiming up to 10°C lower GPU temperature, up to 22% additional FLOPs/W at normal ambient and up to 15% token throughput gain in hot data halls, explicitly positioned as complementary to existing air and liquid cooling; Coherent launched bondable diamond in January 2026, engineered to bond directly to semiconductor die and eliminate the thermal interface material. One distinction deserves emphasis, because it is routinely blurred: what is entering AI servers today is mostly package-level diamond spreading, not monolithic GaN-on-diamond integration, which remains concentrated in RF and defence supply chains.

05Single crystal versus polycrystalline: the dividing line is near-interface conductivity

Polycrystalline diamond wins on size and cost: Element Six's handbook documents free-standing polycrystalline wafers up to 120 mm in diameter, and up to 140 mm in finer-grain material, whereas the same handbook lists routinely available single crystal at the 8 x 8 x 2 mm scale. But thermal management is not decided by a bulk datasheet number; it is decided by the few microns adjacent to the heat source. In polycrystalline films, grain size increases monotonically from the nucleation side toward the growth side, so the near-interface region is grain-boundary dense and phonon-scattering dominated, with conductivity far below bulk. A concrete anchor: Malakoutian et al. (ACS Applied Materials & Interfaces, 2021) grew >2 µm of polycrystalline diamond on GaN with roughly 1.9 µm lateral grain size and measured, by transient thermoreflectance, a grain thermal conductivity of 638 ± 48 W/m·K — around a third of the >2000 W/m·K quoted for bulk thermal grades. Hence the selection rule. Small-area, ultra-high-flux, near-junction problems — RF power amplifiers, laser diodes, extreme hot spots — favour single crystal, where near-interface conductivity cannot be traded away. Large-area lateral spreading with cost pressure and tolerance for a thicker spreader favours polycrystalline. The lid-level requirement in AI accelerators falls awkwardly across both: large area and a bondable, low-resistance interface at once. That intersection is exactly where single-crystal size capability is being revalued.

06The real bottlenecks: TBR, a nanometre-wide bonding window, size and cost

If you remember one number, remember how much of the thermal budget the interface owns. The 2023 Micromachines review reports that up to 50% of channel temperature rise in GaN HEMTs can originate from the thermal boundary resistance to the substrate, and the representative values it compiles span a wide range: around 220 m²K/GW with no interlayer, falling to roughly 6.5–9.5 m²K/GW with a ~5 nm SiN interlayer, against a record of about 3.1 m²K/GW — the 3.1 ± 0.7 m²K/GW reported by Malakoutian et al. in 2021, with diamond grown to within ~1 nm of the channel without degrading its electrical behaviour. The bonding route's process window is narrower than intuition allows: Xu et al. (arXiv:2404.15738, 2024) used surface-activated bonding with a hybrid SiOx-Ar ion source to reach 8.3 m²K/GW across a directly bonded GaN/diamond interface with a 2.5 nm interlayer — and measured 34 m²K/GW, roughly four times worse, when that layer was doubled to 5.3 nm. Set that against amorphous silicon nitride's own 1–1.9 W/m·K and the conclusion writes itself: any 'apply an adhesive and press' approach consumes the entire diamond advantage. The genuine bottlenecks are therefore four: reproducibility of TBR, nanometre-scale bonding and metrology capability, single-crystal size and finishing (polish, flatness, metallisation adhesion), and yield loss from CTE-driven stress. Diamond is not the limitation. The interface is.

07What this means for material suppliers: the spec language is being rewritten

If the above holds, the axes of competition on the material side change. Thermal customers do not qualify parts in carats, colour and clarity; they qualify thickness tolerance, surface roughness and flatness, residual stress and dislocation distribution, metallisation adhesion, a directly bondable surface condition, and lot-to-lot consistency with traceability. When Coherent productises TIM-free direct bonding, it is effectively moving responsibility for the interface upstream, from the customer to the material supplier — a rise in the capability threshold, not merely incremental order flow. As an industry trend judgement rather than a promise: with gem-grade lab-grown prices under sustained pressure, migrating capacity toward industrial applications is rational, but the two businesses are not interchangeable. Jewellery is sold on grading certificates; thermal management is sold on demonstrated process capability and inline metrology. If package-level diamond produces repeatable TCO data in AI servers, demand will first land on large-area bondable single-crystal plates and optical-grade windows, not immediately on GaN-on-diamond epiwafers. The counter-risk should be stated too: if production-scale TBR repeatability cannot be held near design values, or if large single-crystal cost declines more slowly than competing paths such as advanced liquid cooling and microfluidics improve, the curve slips. That is a technical judgement, not a schedule.

08Where ENTASK sits in this chain

Finally, our own coordinates — confirmed facts only. Xi'an ENTASK Semiconductor Technology (founded September 2020, registered capital RMB 20 million) is both an MPCVD equipment manufacturer and a diamond material producer, owning both the systems and the process, so the process window is ours to adjust. On the equipment side we develop the E-MG010K microwave generator (2450 MHz, 10 kW/15 kW): the 10 kW configuration supports a 92 mm growth area with 12 mm crystal growth height, the 15 kW configuration a 120 mm growth area. Systems ship with InsightAction and WiseAction intelligent control, chamber pressure stability of ±0.005 kPa, MTBF above 10,000 hours, over 1,500 hours of continuous fault-free operation at full load, single-run yield of 99% or better, 200–300 ct per machine per month, and a single-run record of 856 ct set in January 2026. On the material side, our thermal products are single crystal only — no polycrystalline: single-crystal heat spreaders at 1800–2500 W/m·K (supplier-stated range; measurement temperature and method per the accompanying report — note Element Six specifies >1900 W/m·K for single-crystal MCC and >2000 W/m·K for its top polycrystalline grade at 300 K, and values roll off with temperature) in sizes from 20 x 20 to 30 x 30 mm; single-crystal optical windows from 20 x 20 to 45 x 45 mm with customisable thickness of 0.5–1.2 mm; non-standard rough up to 30 x 30 x 15 mm and 35 x 35 x 12 mm. We hold ISO 9001:2015 certification and two published patent applications (published by CNIPA; not yet granted), CN119269411A (360° stress analyser for transparent crystals) and CN120178750A (industrial communication system for semiconductor equipment), and supply mainland China alongside India, the Middle East, Europe and North America. To be explicit about scope: we do not build GaN-on-diamond devices or bonding processes. What a material supplier can contribute to this chain is size, consistency and a tunable process — which happen to be the upstream preconditions for every bottleneck described above. (The ENTASK specifications and performance figures below are supplied by the company and have not been independently verified by a third-party test house; buyers should inspect the raw records on site.)

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